* Fast Settling Output Current − 70 ns
* Full-Scale Current Prematched to "1.0 LSB
* Direct Interface to TTL, CMOS, ECL, HTL, PMOS
* Relative Accuracy to .
flexibility.
Advanced circuit design achieves 70 ns settling times with very low glitch and at low power consumption. Mo.
Pin # N Package / D Package 1/5 2/6 3/7 4/8 5/9 6/10 7/11 8/12 9/13
10/14 11/15 12/16 13/1 14/2 15/3 16/4
Symbol
VLC IO V−
IO B1 B2 B3 B4 B5 B6 B7 B8 V+
VREF+ VREF− COMPEN
Description Logic Control Voltage Inverted Output Current Negative Power Sup.
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